This invention relates generally to integrated circuit processing and more particularly to methods for etching via holes in a dielectric layer of an integrated circuit.
Integrated circuits are formed on a semiconductor wafer by subjecting the wafer to a number of processing steps. These processing steps include the deposition of various types of layers, the formation of masks over such layers, the etching of the layers through the masks, the doping of layers, etc. After the integrated circuits are formed, the wafer is cut into a number of dies, each of which includes an integrated circuit, and the dies are then packaged to complete the integrated circuit assembly.
An important processing step is the formation of vias through a dielectric layer which separates two conductive and/or semiconductive layers. Via holes are formed by first covering the dielectric surface with a photoresist mask typically provided with a great number of openings and then etching the dielectric surface through the mask openings. A conductive material, such as aluminum, is then deposited over the surface and within the via holes. Finally, the conductive material over the surface is fully or partially removed to leave conductive vias through the dielectric surface.
A prior art method for forming vias will be discussed with reference to FIG. 1a which shows a substrate layer S.sub.a, a dielectric layer D.sub.a, and a via hole V.sub.a. A conductive layer L.sub.a is typically formed by a sputter deposition process within a commercially available plasma sputter system available from such companies as Varian Associates, Inc. of Palo Alto, Calif. and Applied Materials, Inc. of Santa Clara, Calif. The sputtering process causes ionized atoms of an inert gas, such as argon, to strike an aluminum target, thereby dislodging aluminum atoms from the surface of the target, some of which will settle over the surface of dielectric layer D.sub.a and within the via hole V.sub.a. As indicated by the arrows in FIG. 1a, the aluminum (Al) atoms can settle on the surface D.sub.a and within the via V.sub.a from a number of directions.
A problem encountered with this prior art method for forming vias is the so-called shadowing effect where the rim of the via hole V.sub.a can block angularly moving aluminum atoms from depositing within certain portions of the via holes. For example, in FIG. 1a, some aluminum atoms travelling angularly downwardly from left to right may be blocked by the left-side rim of the via hole V.sub.a, while some aluminum atoms travelling angularly downwardly from right to left may be blocked by the right-side rim of the via hole. This tends to cause uneven deposition within the via hole V.sub.a, creating a via having pronounced cusps C.sub.a. These cusps are weak points in the via and can fracture, breaking the electrical connection through the via. Furthermore, as the via fills and the sidewalls of the via grow together, a void may form within the via which can be a further cause of potential failure of the via.
A prior art structure which reduces the shadowing effect in via holes is illustrated in FIG. 1b. This prior art structure includes a substrate layer S.sub.b, a dielectric layer D.sub.b, a via hole V.sub.b, and a conductive layer L.sub.b, where the rim of the via hole V.sub.b is beveled or tapered as shown at T.sub.b so that fewer of the angularly moving aluminum atoms are shadowed by the rim of the via hole. This reduced shadowing results in much smaller cusps C.sub.b and more uniform deposition within the via hole V.sub.b.
A method for forming the prior art tapered rim via hole structure will be discussed with reference to FIG. 1c which shows a substrate layer S.sub.c, a dielectric layer D.sub.c and a masking layer M.sub.c. The masking layer M.sub.c includes a number of openings O.sub.c which correspond to the locations at which via holes are to be formed. As a first step, a recess R.sub.c is isotropically etched through the openings O.sub.c as illustrated in the left side of the figure. This isotropic etch is typically a "wet etch", i.e. is accomplished with a liquid acid such as hydrofluoric (HF) acid. Wet etching tends to be omnidirectional, and therefore causes undercutting of the mask layer M.sub.c to form tapered surfaces T.sub.c. This wet, isotropic etch is then followed by an anisotropic etch to form the main body of the via hole, as illustrated on the right side of FIG. 1c. This anisotropic etch is typically a "dry etch", i.e. is accomplished within a plasma etch system which creates the nearly vertical sidewalls of a via hole V.sub.c.
As the feature sizes of integrated circuits shrink, the diameters of via holes become correspondingly smaller, making it increasingly difficult to cause liquid acid to flow into the openings O.sub.c of the mask layer M.sub.c due to the surface tension of the liquid and due to residual air bubbles trapped within the openings O.sub.c. Therefore, the wet etch portion of the prior art process for forming via holes with tapered rims is poorly adapted for the latest generations of very large scale integrations (VLSI) and ultra large scale integration (ULSI).
Another problem encountered with the wet etch process is particulate contamination. Even the purest of liquid etchants include many fine particles which can adhere to portions of the integrated circuit and possibly destroy the functionality of the integrated circuit. Since these particles are very difficult to filter out, each wet etch process adds statistically to the failure rate of each integrated circuit die, thereby reducing the yield of functioning integrated circuits per wafer.
The wet etch process also requires a subsequent water rinse and dry cycle to remove the remaining acid. Since even the purest of distilled water contains some contaminants, the rinse and dry cycle also adds particulate contamination of the wafer with a subsequent reduction in the yield of functional integrated circuits per wafer.